Referring to FIG. 1 showing a PLL, the PLL comprises a phase frequency detector 10, a charge pump 20, a loop filter 30, a VCO 40 and a frequency divider 45. A reference signal with a reference frequency Fref is generated by a reference oscillator (not shown), and is inputted simultaneously into the phase frequency detector 10 along with a frequency divided signal from the frequency divider 45. The phase frequency detector 10 detects a phase and frequency difference between the reference signal and the frequency divided signal, and it then outputs a phase difference signal to the charge pump 20. The charge pump 20 then generates an output current having a value associated with the phase difference signal and fed to the loop filter 30, resulting in an output signal having an amplitude corresponding to the phase difference signal. The loop filter 30 smoothes the output current and converts it to a control voltage Vctrl fed to the VCO 40. The VCO 40, according to the control voltage Vctrl, generates a voltage controlled signal having a voltage controlled frequency Fvco, which is then divided using the frequency divider 45 by N to generate the frequency divided signal upon receiving the voltage controlled signal, where N may or may not be an integer and Fvco=N*Fref.
The VCO 40 typically has two types, an LC oscillator and a ring oscillator. To enable the VCO 40 to operate with a higher adjustable frequency range, the VCO includes a bank of switched capacitors. The switched capacitor bank or capacitor DAC is controlled with a digital control word to shift the VCO frequency so that the VCO 40 can provide a plurality of frequency tuning curves for adjusting the voltage controlled frequency Fvco of the voltage controlled oscillator. FIG. 2 showing a relationship diagram of a control voltage Vctrl and a voltage controlled frequency Fvco of a conventional VCO.
With reference to FIG. 2, the control voltage Vctrl of the voltage controlled signal has a linear control range, i.e., the range between VL and VH. When the VCO operates on curve 1, the voltage controlled frequency Fvco of the VCO varies between the range of F1L and F1H. When the VCO operates on curve 2, the voltage controlled frequency Fvco of the VCO varies between the range of F2L and F2H. When the VCO operates on curve 3, the voltage controlled frequency Fvco of the VCO varies between the range of F3L and F3H. When the VCO operates on curve 4, the voltage controlled frequency Fvco of the VCO varies between the range of F4L and F4H. More specifically, the voltage controlled frequency Fvco of the VCO in FIG. 2 may cover a range from F1H to FNL, where N is the number of digitally controlled switched capacitors in the circuit. Therefore, it is concluded that the variable range of the voltage controlled frequency Fvco increases as the number of curves provided by the VCO increases.
In order to maintain a stable voltage controlled frequency Fvco when operating the PLL in an environment where the ambient temperature varies over a relatively large range, the control voltage Vctrl also needs to vary with the temperature variance. For example, FIGS. 3A and 3B are schematic diagrams of the control voltage Vctrl and the voltage controlled frequency Fvco when a VCO of a same PLL operates under different temperatures T1 and T2. Suppose the VCO selects curve 3 as its operating band, VL=1V and VH=2V, and the voltage controlled frequency Fvco is fixed at 4 GHz, and T1<T2. FIG. 3A shows the relationship diagram at the temperature T1, when the control voltage Vctrl is at 1.5V, the voltage controlled frequency Fvco of the VCO may operate at 4 GHz. Note that, accompanied with increase in temperature, all bands of the VCO shifts downwards. Hence, as shown in FIG. 3B, to maintain the VCO frequency at the new temperature, T2 the locked PLL automatically adjusts the control voltage Vctrl to 1.9V. If the temperature continues to rise to a higher temperature, the control voltage Vctrl shall also adaptively increase until it reaches the maximum range of the voltage controlled capacitance (2V in this example). Once the control voltage Vctrl exceeds the linear control range, it causes the PLL to lose lock.
As described above most PLLs with an LC VCO require two tuning inputs. There is a digital coarse tuning input that drives a bank of switchable capacitors; and there is an analog fine tuning input that drives a varactor. During coarse tuning (CT), the analog fine tuning input is held constant by a voltage digital analog converter (DAC) and the PLL is locked using only the digital coarse tuning VCO input. The turning algorithm eventually converges to the most likely coarse tuning curve and the PLL is considered coarse locked. The PLL then enters fine lock (FL) mode. During this mode, the PLL CT inputs are held at the converged upon value from the previous state and the analog fine tuning input is driven by the PLL loop filter rather than the voltage DAC. In this mode, the PLL will remain locked as long as the fine tuning range of the VCO is not exceeded. The PLL will also track any VCO frequency transient as long as it is within the bandwidth of the PLL.
If a temperature transient causes the VCO frequency to decrease, the PLL will have to push the analog fine tuning voltage higher to keep the PLL locked at the same frequency. Certain electronic communications, such as the wideband code-division multiple access (WCDMA TX/RX), require that the PLLs lock and potentially remain locked for a very long time period without any allowable interruption. Thus, it is the objective of the current invention to provide a system that allows the PLLs to remain fine locked during the large temperature transient or any other outside influences.
The U.S. Pat. No. 4,978,930 issued to Suter discloses a low voltage VCO temperature compensation circuit. Suter discloses a varactor VCO circuit, and Suter's varactor VCO circuit calculates an offset value between a PTAT current and a temperature stable current, and provides the offset value to control the VCO varactor. Suter's invention assumes that the entire temperature variation of the VCO must be supported by the varactor turning range.
The U.S. Pat. No. 5,831,482 issued to Salvi discloses a method and apparatus for self-tuning a VCO. Salvi discloses a VCO with two analog inputs. Salvi discloses a coarse tuning employing a comparator comparing the VCO control voltage to a reference voltage. Salvi's comparator outputs the result into a 4-bit register that drives a DAC. The DAC drives a loop filter that drives a second analog tuning voltage input. Salvi discloses that the circuit only operates for a predetermined number of clock cycles. Salvi's circuit does not operate after the initial tuning and Salvi does not disclose a continuous monitoring and compensating the tuning signal.
The U.S. Pat. No. 6,342,798 issued to Yoshida discloses a PLL circuit with a temperature compensated VCO. Yoshida discloses an open loop temperature compensating circuit. Yoshida discloses an external control voltage to the VCO as an input in range of the phase comparator. With this external control voltage, Yoshida provides a stable PLL operation regardless the change of the ambient temperature. Yoshida does not disclose any feedback loop connecting to the temperature variable voltage source.
The U.S. Pat. No. 7,164,325 issued to Aparin discloses a temperature stabilized voltage controlled oscillator similar to Yoshida patent above. Aparin discloses compensating temperature change by applying a temperature variable voltage source, such as a proportional to absolute temperature (PTAT) device, to varactors of the VCO resonant circuit. Aparin does not disclose any feedback loop connecting to the temperature variable voltage source.
The U.S. Pat. No. 6,545,547 issued to Fridi discloses holding the main varactor at a set voltage during the coarse tuning. Fridi discloses hybrid digital coarse VCO turning and VCO temperature drift compensation providing for a fully digital tuning scheme without the need for charge pumps. Fridi discloses setting and correcting a digital VCO coarse tuning code by comparing an N divider output to a fixed timer clock. The N divider content is used to set the next VCO coarse turning code. Fridi divides the coarse tuning process into two phases: an open loop phase and a closed loop phase. Once a new channel is selected by a device using the PLL, a control signal will open the loop via a first switch and set the VCO analog control line to a reference voltage through a second switch. Fridi assumes that the entire temperature variation of the VCO is accounted for in the main varactor range, and Fridi does not discloses any continuous monitoring and compensating after the coarse tuning.
In view the conventional practices, there is a need to continuous monitoring the VCO frequency and to compensate the VCO control voltage independently from the PLL based on the monitoring result; hence, the PLL can remain fine locked. The current invention provides a novel design to allow a PLL to remain fine locked during a large temperature transient. Furthermore, the current invention provides a system and a method selectively to compensate the temperature change or to tune the VCO based on a bandgap referenced voltage.